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L2 cache and system memory
The L2 cache is equal to 2MB organized in 16-way. The second-level TLB is 1024 pages 8-way and serves both data and instruction caches. The L2 prefetchers are multiple and can have up to 23 outstanding transactions to memory.
The L3 cache is also 8MB organized in 4 banks of 2MB and is shared between the 4 modules. It's a victim cache, which contains the data that must be removed from the L2 cache of the various modules, to make room for new data. It works the same frequency as the North Bridge, which also operates four HyperTransport controller and a dual channel DDR3 memory controller that supports up to 4 memory modules and memory up to 1866 MHz.
Supported instructions
The instructions supported by Bulldozer are SSE up to 4.1 and 4.2 included, the 256-bit register AVX, instructions for the AES encryption acceleration, and 4-operand nondestructive FMA instructions (XOP instruction set).
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